Lauterbach expands tools for RISC-V designs

Lauterbach expands their CombiProbe family of combined debug and trace units to support the RISC-V architecture. 

All Lauterbach RISC-V debug tools are designed to work with the latest ratified RISC-V debug specification. The CombiProbe supports both 32bit and 64bit RISC-V cores and is designed to debug mid-range systems, which typically feature multiple heterogenous cores. Support is included for a medium bandwidth trace port of up to 400MBits/s per channel for 4 channels, for the already existing proprietary “SiFive Nexus Trace” and for future trace specifications once they are formally ratified by RISC-V International. A typical use case might be a RISC-V and a pair of Cortex-M cores in the same SoC. The TRACE32 PowerView software includes a well-documented API, allowing users to extend the disassembler to support custom instructions. The CombiProbe will interface to a 20-pin ‘Arm standard’ debug header or the RISC-V defined MIPI10 and MIPI20T headers. 

RISC-V is an open Instruction Set Architecture that allows designers to create chips with a well-defined instruction set, custom peripherals, yet remain royalty free. Originally developed at UC Berkely in 2010, today it is maintained by the non-profit RISC-V International Consortium. The RISC-V specification allows for 32-bit (RV32), 64-bit (RV64) and 128-bit (RV128) instruction sets with a number of ratified extensions to add functionality such as: floating point, atomic operations, multiplication, compressed instructions, and standard debug, etc. 

According to Norbert Weiss, Managing Director or Lauterbach GmbH, “We see RISC-V as becoming a significant influence in the future of embedded systems. The designs cover a broad range of applications and customers can be assured that there will be an appropriate TRACE32 tool for their designs to help them get to market more quickly and with higher quality code.” 

The CombiProbe support for RISC-V will be available from 1st January 2021.

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